my-solutions/advent-of-code/2024/day_09/Makefile

19 lines
365 B
Makefile

TARGET_EXEC := main
BUILD_DIR := ./build
CFLAGS := -Wall -Wextra -g
SRCS := $(shell find . -name '*.c')
OBJS := $(SRCS:%=$(BUILD_DIR)/%.o)
# The final build step.
$(BUILD_DIR)/$(TARGET_EXEC): $(OBJS)
$(CC) $(OBJS) -o $@
# Build step for C source
$(BUILD_DIR)/%.c.o: %.c
mkdir -p $(dir $@)
$(CC) $(CFLAGS) -c $< -o $@
.PHONY: clean
clean:
rm -r $(BUILD_DIR)